Current limits for User FPGA pins

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#1

Please help me find the max current specs for the User FPGA pins. As a complete novice to FPGAs, I want to wire up 8 LEDs and, hopefully, figure out how to make a binary counter.

I think the Lattice ICE data sheet is saying I can draw maybe 3 pins at 24 mA each so total of 72 mA. So if I throttled 8 LEDs down to 5 mA per (which can still easily be seen using high quality blue LEDs), such a circuit should be OK.

Thanks in advance.

#2

Hi @robr,

I don’t know which blue LEDs you’re using, but the ones I have need 3.4v which is a little higher than the FPGA’s outputs. And, as you noted, you only get three high-current outputs. A LED driver chip such as the TLC5947 might work better for you.

You may also need a level shifter to drive the chip. Here’s a tutorial on level shifting to explain what’s involved.

1 Like
#3

Hi @sarahclark,

Thank you, I had completely forgotten about LED bandgap.

All I’m trying to learn right now is to blink a single external LED but modifying the example Blinky.v program gave me compile errors. So, after poking around on web I tried this, but still no blink. Now have removed red LED and just looking at PC board pin 14 (FPGA 36) with Saleae probe. No toggling. I would think that the counter in rolling over would be toggling the state and therefore the FPGA pin.

// WF_blinkExternalLED.v
// rr August 25, 2019
// @map_IO LED_1 36

module fpga_top(output wire LED_1, input wire WF_CLK);
reg [24:0] counter;
reg state;

assign LED_1 = state;

always @ (posedge WF_CLK) begin
    counter  <= counter + 1;
    state <= counter[24];

end

endmodule

#4

There’s a special set of driver functions defined for controlling the RGB LED outputs. See https://github.com/cliffordwolf/icestorm/blob/master/icefuzz/tests/sb_rgba_drv.v (as WebFPGA uses ice storm for synthesis IIRC.)

P.S. Did you want a 25 bit counter or a 24 bit one?

#5

robr,

You can turn on 20ma type LEDs with the IOs. I would use 220 to 330 ohm resistor in series to 3.3v. Don’t use 5v as you will exceed the FPGA max IO voltage.

3.3v
 -------
    |
    |
   / 
   \
   /   330 ohms
   \
   |
   |
_____
\     /
  \ /
-------
   |
   |
   |____  to IO pin.

Sorry for crude drawing, I can put it in a proper schematic form and take a snapshot latter tonight.

Also when you use @MAP_IO xxxx

xxx is the label on the ShastaPlus, the website will translate this to the actual FPGA pin. So you used 36 which isn’t valid, use 14.

mick

#6

mick,

Thank you. No need for schematic. 330 ohm from 3.3V to red LED anode, turns on when cathode grounded.

Pin 10 on ShastaPlus PC board works driving 7 segment display. But the following code must have something wrong as it does not toggle pin 10 (User FPGA 28) when connected to LED

Not surprising as I am a complete beginner with Verilog.

// #CAS_IO LED_1 28
// @map_IO LED_1 10

module fpga_top(output wire LED_1, input wire WF_CLK);
reg [24:0] counter;
reg state;

assign LED_1 = state;

always @ (posedge WF_CLK) begin
counter  <= counter + 'b1;
state <= counter[24];
end

endmodule

#7

Hey can you cut paste the start of the synthesis output from the web status window. The pcf (pin control file) object is displayed. @map_IO should be @MAP_IO.

mick

#8

Also I will eliminate the #CAS_IO directive, its old from initial dev, from the examples. No need to add confusion.

Mick

#9

YEA! YES! It works. Doing MAP rather than map made the difference. Took out the #CAS directive. Even a blue LED works.

Thank you all for helping me get my first program to finally work.