I tried lattice’s tools directly and the same error occur. I haven’t run with the open source tools yet.
This is the full error.
E1216: Routing of net CLK_c Failed. Source : T_19_31_wire_io_cluster/io_0/gbout, Sink : T_21_1_wire_logic_cluster/lc_3/clk
Not too enlighting.
I have opened a case with lattice and will update if they give a response.
I did try some things and was able to generate a bit file with the clock at webFPGA pin3.
I manually instantiasted the CLK inputs. Here is the code:
// Setting CLK to pin 3 causes “Routing of Design: Failed”
// This works if the pin is set to something like 6
// @MAP_IO CLK 3
// @MAP_IO RQ0 5
// @FPGA_TOP ripple_counter_da
output reg Q
Q <= D;
.PIN_TYPE(6’b000001), // input
// assign clock_in = CLK;
d_flop ff0(.D(~RQ0), .CLK(clock_in), .Q(RQ0));
Can you try it on real h/w to see if it works, or not?
It isn’t a pretty solution for educational classes, but if someone runs into this type of problem with the s/w tools and they had laid out real h/w with that pin being the clock, then they should be able to proceed without redesigning the PCB. It seems to be a tool problem not a FPGA resource issue.