| Topic | Replies | Views | Activity | |
|---|---|---|---|---|
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WF_XXX Internal Pin Aliases (and @MAP_IO Help)
Intro First, I want to clarify that there are two sets of pins when discussing the main FPGA device. EXTERNAL The physical pins that run along the perimeter of the FPGA device’s PCB. INTERNAL The small pins that sur… |
|
405 | 7 | July 20, 2020 |
|
Linux udev Rules
Hi all, For Linux support, you need to add a udev rule for read/write permission for the USB device. # Store the file here: # /etc/udev/rules.d/60-webfpga.rules # # Run this command to reload the udev rules without r… |
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332 | 4 | September 22, 2019 |
| Issue with command line synthesis (Ubuntu in VirtualBox) |
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18 | 4 | January 6, 2021 |
| Trouble connecting Ubuntu VM |
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20 | 6 | January 3, 2021 |
| Beginner Project toggle IO pins |
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292 | 6 | December 7, 2020 |
| Doesn't like clock on pin 3? Routing of Design: Failed |
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43 | 3 | October 10, 2020 |
| Misunderstanding bitwise OR? |
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113 | 2 | April 27, 2020 |
| Further chapters of the book? |
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109 | 2 | April 27, 2020 |
| Board shows up as unrecognized |
|
98 | 2 | April 27, 2020 |
| Verilog Demo Connections for the Kit |
|
437 | 5 | February 26, 2020 |
| FPGA board pinout (ShataPlus) |
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314 | 2 | October 24, 2019 |
| WebFPGA Documentation book |
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278 | 2 | January 14, 2020 |
| Windows Supported? |
|
414 | 10 | January 5, 2020 |
| Broken Component? |
|
142 | 2 | November 6, 2019 |
| Programming language |
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337 | 7 | November 2, 2019 |
| WF_Blinky_with_switch.v Questions |
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170 | 2 | October 23, 2019 |
| FPGA 10kHz oscillator |
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263 | 6 | October 23, 2019 |
| Closeup photo of unit with breadboard pin headers soldered on? |
|
198 | 3 | October 22, 2019 |
| FPGA 48 MHz oscillator |
|
199 | 3 | October 21, 2019 |
| How to use command-line flow (IceStorm or Cloud Synth) |
|
846 | 23 | January 4, 2021 |
| Making the project open source |
|
236 | 5 | October 14, 2019 |
| Platforms that support WebUSB [link to info] |
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166 | 1 | September 17, 2019 |
| Are you sure about the breadboard pin layout? |
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226 | 3 | September 5, 2019 |
| Command line build under windows |
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178 | 4 | September 4, 2019 |
| How can we drive the PLL? |
|
259 | 9 | September 2, 2019 |
| Generating or using a reset signal |
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514 | 6 | September 1, 2019 |
| Current limits for User FPGA pins |
|
198 | 9 | August 27, 2019 |
| Nice job, bravo |
|
163 | 1 | August 25, 2019 |
| Quick Start Guide |
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240 | 2 | August 21, 2019 |
| Tools location, and a Chromium programming issue |
|
182 | 3 | August 11, 2019 |
