Error using WF_timer module

Verilog/VHDL Help
#1

The error it generates is “net pwr is constantly driven from multiple places at instance ten_usec, on port enable. VDB-1000”.
Any ideas as to what my code is doing wrong?:

module fpga_top(
input wire WF_BUTTON,
input wire WF_CLK,
output wire WF_LED
);
WF_timer #(.COUNT(159), .EVERY_CLK(1’b1)) ten_usec(
.clk(WF_CLK),
.enable(1’b1),
.timer_pulse(ten_us)
);
assign WF_LED = WF_BUTTON;
endmodule

#2

Hi DaveW,

Are you using the website or the command line interface?

I didn’t see the WF_timer module included in your verilog.
See WF_blink_with_switch.v, which uses the timer module to debounce the push button switch.

Also you need to use at least one output of an instantiated module, that may have caused a 1’b1=1’b1 condition which maybe the error reference. I wasn’t able to dup[licate the error yet.

//////////////////////////////////////////////////////////////////////
//
// timer
//
module WF_timer (
input wire clk,
input wire enable,
output reg timer_pulse
);

parameter [9:0] COUNT = 499;
parameter EVERY_CLK = 1’b0;

reg [9:0] counter;

always @ (posedge clk)
    if (enable)
      begin
        if (counter == COUNT)
          begin
            timer_pulse <= 1'b1;
            counter     <= 'b0;
          end
       else
         begin
          counter     <= counter + 'b1;
          if (EVERY_CLK)  // case enable never goes low
           timer_pulse <= 1'b0;
         end

      end
    else
        timer_pulse <= 1'b0;

endmodule