I ran into an EE student that was using an FPGA to test breadboard circuit designs and thought that was a pretty good idea, and that it might be a good way to get some practical Verilog experience. But I am having a hard time thinking through the approach and was hoping someone here might have some suggestions.
What I am thinking about is something like how a TL866II plus programmer has logical tests for most of the common IC chips you used in breadboard layouts. They are just simple logic tests to verify the chips are good. I’m thinking about something like this, but setup based on testing whatever breadboard design I am working on.
Does this seem possible? I don’t see how to do it, but I think it would be a great resource and use for the ShastaPlus. I was thinking it might be some sort of state machine… of sorts.
For example, I am building an 8-bit computer (eater.net) on a breadboard and I having trouble with the registers. So, I want to test the registers to make sure they are good before I move on. To do this, I need to setup 8 input pins and 8 output pins, as well as a clear, load, clock, and enable pins. I setup the ShastaPlus and wired it all up to the board, but I’m not really sure where to start. I’m not sure how best to run a test via Verilog.
What I am trying to do would be something like…
- Enable clear
- Disable clear
- Set various input pins to high… say 
- Load - reads 8 input pins into register
- Disable load
- Enable output
- Verify the 8 output pins match the 8 input pins.
What this would test is that the enable, clear, load, and flip-flops are all working as expected. I know that they are not in this case, as I am using TI 173 ICs manufactured in different countries and the open pins float differently. One floats down and one floats up. I want to setup a test and verify the thing works, which it will not, then add pull-down resisters to verify that solves the issues. I can certainly just test this manually, but I would like to have a simple test I can hook up and run anytime I want to make sure everything is still good.
The only thing I can think of is to use the clock and maybe a variable to identify the current step. Then [using always @(posedge WF_CLK) begin] and a CASE statement, I might be able to control the flow of the test. But I don’t know if this is the correct approach or not.
I’m hoping someone knows how this is actually done might offer some suggestions.