ShastaPlus to test Breadboard Designs

I ran into an EE student that was using an FPGA to test breadboard circuit designs and thought that was a pretty good idea, and that it might be a good way to get some practical Verilog experience. But I am having a hard time thinking through the approach and was hoping someone here might have some suggestions.

What I am thinking about is something like how a TL866II plus programmer has logical tests for most of the common IC chips you used in breadboard layouts. They are just simple logic tests to verify the chips are good. I’m thinking about something like this, but setup based on testing whatever breadboard design I am working on.

Does this seem possible? I don’t see how to do it, but I think it would be a great resource and use for the ShastaPlus. I was thinking it might be some sort of state machine… of sorts.

For example, I am building an 8-bit computer ( on a breadboard and I having trouble with the registers. So, I want to test the registers to make sure they are good before I move on. To do this, I need to setup 8 input pins and 8 output pins, as well as a clear, load, clock, and enable pins. I setup the ShastaPlus and wired it all up to the board, but I’m not really sure where to start. I’m not sure how best to run a test via Verilog.

What I am trying to do would be something like…

  1. Enable clear
  2. Disable clear
  3. Set various input pins to high… say [00010001]
  4. Load - reads 8 input pins into register
  5. Disable load
  6. Enable output
  7. Verify the 8 output pins match the 8 input pins.

What this would test is that the enable, clear, load, and flip-flops are all working as expected. I know that they are not in this case, as I am using TI 173 ICs manufactured in different countries and the open pins float differently. One floats down and one floats up. I want to setup a test and verify the thing works, which it will not, then add pull-down resisters to verify that solves the issues. I can certainly just test this manually, but I would like to have a simple test I can hook up and run anytime I want to make sure everything is still good.

The only thing I can think of is to use the clock and maybe a variable to identify the current step. Then [using always @(posedge WF_CLK) begin] and a CASE statement, I might be able to control the flow of the test. But I don’t know if this is the correct approach or not.

I’m hoping someone knows how this is actually done might offer some suggestions.

Best regards,

Hi Jon,

ShastaPlus can be used to test and IC. Even a microcontroller could do it as well, the FPGA approach would be able to test at a higher speed.

Your approach outlined is pretty close to standard IC testers used in production.
For the DUT (device under test) you would use asserts to drive the inputs and capture the outputs. The output vector would be compared to the expected results to determine a pass/fail. You can then modify the pullup/pulldowns, rerun the test vectors to see if the problem is resolve. For debugging the captured vectors can be downloaded and displayed in a graphical form and analyzed.

For the FPGA coding, I would suggest an assert ROM for the input vectors, and a compare ROM for the captured outputs to be compared to. ShastaPlus has a large number for RAM blocks that can be configured into ROMs. Then a simple state machine would step at some multiple of the DUT clock driving the inputs and capturing the outputs.

There are a lot of nuances , esp. with tristated pins and for don’t cares on the outputs. For a simple IC these likely won’t apply.

Generating the assert ROM and capture ROM is straight forward. I am assuming you simulated your IC, so adding into your simulation environment a module to capture the assert vectors and expected vectors is all what is needed. Just export the captured sim vectors into the required ROM format and add those to the FPGA code base.