Names of Pins of Pins?


I've been playing with WebFPGA & my shasta+ card.  Working through some of the simpler programs to teach myself a bit of Verilog.  The Web IDE seems to be a bit more reliable than the last time I tried it.  But it still crashes if I abuse it too much.

Abuse it?
One of the standard things I do when I play with a new computer language is to throw syntax errors at it and see what happens. Things like extra semicolons, missing keywords, misspelled variables …etc. That way, the errors aren’t quite as cryptic when I really need them.

Right now, I’m trying to access the pins around the perimeter of the Shasta+. Looking at the sample programs, I’ve discovered the following names that might or might not be external pins:



I modified WF_blinky.v to output an easily scopable waveform of a couple kilohertz. Then tried likely names to get to an external pin. I had great hopes for CPU0 - CPU3, but no joy. I suspect those are lines between the FPGA and the USB-interface CPU.

Where can I find a canonical list of the I/O pins? With names that can be used in a program?

         - Jerryk

I added code to set ALL of the pin names ( that I know ) to the output square wave. Getting output on pins 00, 01, 03, 04, 05, 06, 07, 09, 10, 15 and 27.

OK, “LOAD” = pin 15.
“MCLK” = pin 10
“LRCK” = pin 15
“SCK” = pin 04
“SDATA” = pin 04
“MST_OUT_SLV_IN” = pin 01
“MST_IN_SLV_OUT” = pin 03
“RGB_CLK_OUT” = pin 01
“WF_NEO” = pin 01
“RGB_DOUT” = pin 06
“RGB_LOAD” = pin 05
“SIO_MST_OUT_SLV_IN” = pin 25

Now these are of course special purpose names - defined somewhere for a specific project. Do I just get the generic names out of the datasheet for the FPGA?

   - Jerryk

Hi Jerry,

Here is a pointer to ShastaPlus’s pin out.

The above is included in the webfpga doc here as well.
The above link is from the home page under site map.

This forum post should also help explain how to define your desired pinout within the verilog code.


OK, let’s say I want to talk to pin 17 - the pin right next to the top ground wire on the L/H side ( with the USB connector at the top ).

Do I say “output reg pin_17”? or “output reg pin17”? or “output reg PIN_17”? Or “output reg PIN17” ? I tried all of these, no joy.

          - Jerry

Tried the same with pin 23. I see that 17 is shared with the flash. Still no joy.

Hi Jerry,

I modified the blinky.v code to add another IO to show you how to use the @MAP_IO directive to define a user signal to follow the WF_LED signal.

But first, the @MAP_IO directive uses the ShastaPlus PCB silkscreened IO pin number. The backend tools of webfpga takes the @MAP_IO results and maps to the actual FPGA pin. The pin “17” you were using is the FPGA pin number. So with the @MAP_IO directive you use the silked number which is easier.

In my modified code I used the first user IO that is not shared, which is pin 3.

You can cut and paste this code into the webfpga IDE.

// WF_blinky.v   (modified)
// The "Hello World" of Digital Logic!
// This example blinks the on-board user LED once a second.

// @MAP_IO MY_LED      3

module fpga_top(
    input  wire WF_CLK,
    output reg  WF_LED,
    output wire MY_LED

reg [23:0] counter;

// Blink LED every 1000 ms
always @ (posedge WF_CLK) begin
    // Try using a different value here...
    // 8000000 will cause it to blink twice as fast!
    if (counter == 16000000) begin
        WF_LED   <= ~WF_LED;
        counter  <= 'b0;
    end else begin
        counter  <= counter + 'b1;

assign MY_LED = WF_LED;


MY_LED is defined as a wire. WF_LED is defined as a register because it is in a “always” block.


Wow - that actually seems to work. Not sure how. It’s inside a comment. Guess Verilog
comments aren’t quite as ignored by the synthesizer as they are in C. Is it some sort of

Yes, there is a preprocessor to allow for fpga pin assignments.