FPGA 48 MHz oscillator

#1

FPGA 48 MHz oscillator

Here is one way to “see” the FPGA high frequency clock. Four different
frequencies are available by changing the literal in the defparam statement
as listed below in program comments.

// ShastaPlus single pin toggle HF OSC, rr Oct 15, 2019
// PC board pin 14 to saleae; PC gnd to saleae gnd
// Pin 14 monitors one half of HF FPGA oscillator.

// @MAP_IO PIN_14 14

module fpga_top(output wire PIN_14);

reg [0:0] counter; reg state0;
assign PIN_14 = state0;

wire	clk_en = 1'b1;

SB_HFOSC OSC_i (
	.CLKHFEN(clk_en),
	.CLKHFPU(clk_en),
	.CLKHF(clk));
	
defparam OSC_i.CLKHF_DIV = "0b00";
	
always @ (posedge clk) begin
	counter  <= counter + 1'b1;
	state0 <= counter;
end

endmodule

// Lattice Technical Note iCE40 Oscillator Usage Guide
// FPGA-TN-02008 Version 1.4
// pg4: “…SB_HFOSC runs at maximum 48 MHz with output divider
// by 1, 2, 4, or 8”, for clocks at 48, 24, 12, and 6 MHz
// per WF_7seg_clock example, there is a statement:
// defparam OSC_i.CLKHF_DIV = “0b10” for 12 MHz
// note the quotees around the literal

// omitting the defparam statement gives default 48 MHz clock
// “0b00” = a 48 MHz clock or 24 MHz on the pin
// “0b01” = a 24 MHz clock or 12 MHz on the pin
// “0b10” = a 12 MHz clock or 6 MHz on the pin
// “0b11” = a 6 MHz clock or 3 MHz on the pin

QUESTIONS:

1.Why the quotes around the literal?
2. Why the literal width of zero?

#2

Here is a revision which is probably the simplest way to see the FPGA 48 MHz oscillator on a PC board pin. Thanks to help from ryan jacobs

// ShastaPlus FPGA HF pin toggle, rr Oct 16, 2019
// This is probably the simplest code to output the FPGA
// 48 (or 24, 12, or 6) MHz oscillator to a PC board pin
// Thanks to help from ryan jacobs

// @MAP_IO PIN_14 14

module fpga_top(output wire PIN_14);

wire	clk_en = 1'b1;
SB_HFOSC OSC_i (
	.CLKHFEN(clk_en),
	.CLKHFPU(clk_en),
	.CLKHF(clk));
defparam OSC_i.CLKHF_DIV = "0b10"; // divide to 12 MHz
assign PIN_14 = clk;

endmodule

// Lattice Technical Note iCE40 Oscillator Usage Guide
// FPGA-TN-02008 Version 1.4
// pg4: “…SB_HFOSC runs at maximum 48 MHz with output divider
// by 1, 2, 4, or 8”, for clocks at 48, 24, 12, and 6 MHz
// per WF_7seg_clock example, there is a statement:
// defparam OSC_i.CLKHF_DIV = “0b10” for 12 MHz
// note the quotes around the literal

// omitting the defparam statement gives default 48 MHz clock
// “0b00” = a 48 MHz clock
// “0b01” = a 24 MHz clock
// “0b10” = a 12 MHz clock
// “0b11” = a 6 MHz clock

#3

Hi robr,

My answer isn’t going to get to the actual reason since these modules are provided by lattice.
Parameters are constants at runtime/compile time, with width not needed. I couldn’t find in the lattice libraries where they actually use the passed in parameter. So I can only guess why they use 0b as a prefix. “b” is obviously for binary, and the preceding 0 maybe like c-code using 0x for hex. The total quoted value makes it a string. I would guess that the code that actually uses the parameter does some sort of string compare. Many of the cells use that method to pass in parameters. When I use parameters in the WebFPGA library I use just unquoted values that are just substituted in actual verilog code in the parameterized module. Example would be the WF_timer module in the WF_7seg_clock_demo.v