| Topic | Replies | Views | Activity | |
|---|---|---|---|---|
|
WF_XXX Internal Pin Aliases (and @MAP_IO Help)
Intro First, I want to clarify that there are two sets of pins when discussing the main FPGA device. EXTERNAL The physical pins that run along the perimeter of the FPGA device’s PCB. INTERNAL The small pins that sur… |
|
6 | 1486 | July 20, 2020 |
|
Linux udev Rules
Hi all, For Linux support, you need to add a udev rule for read/write permission for the USB device. # Store the file here: # /etc/udev/rules.d/60-webfpga.rules # # Run this command to reload the udev rules without r… |
|
3 | 1659 | September 22, 2019 |
| Error using WF_timer module |
|
1 | 26 | April 10, 2025 |
|
Internal FPGA Resources
|
|
2 | 81 | April 10, 2025 |
|
Build using vscode YoWASP
|
|
0 | 172 | September 11, 2024 |
| Names of Pins of Pins? |
|
7 | 1213 | September 25, 2023 |
| ShastaPlus to test Breadboard Designs |
|
1 | 551 | July 26, 2023 |
|
Support other hardware on the web designer
|
|
1 | 473 | July 26, 2023 |
| Webfgpa is not Synthesizing |
|
7 | 679 | January 18, 2023 |
| Windows Supported? |
|
10 | 1402 | December 17, 2022 |
| Try WebFPGA on Gitpod (VSCode in the browser) |
|
4 | 887 | September 10, 2022 |
| Is there an open-source way to perform compress-bitstream? |
|
6 | 930 | August 26, 2022 |
| GUI Application for WebFPGA |
|
0 | 641 | April 29, 2022 |
| Error: synthesis already running |
|
1 | 610 | March 8, 2022 |
|
HELP! Looking for used board
|
|
1 | 733 | February 9, 2022 |
| Documentation for the microcontroller? |
|
4 | 980 | January 2, 2022 |
|
A CPU for your WebFPGA!
|
|
0 | 663 | September 12, 2021 |
| Recommendation for Simulation Analysis? |
|
1 | 922 | May 14, 2021 |
| Different behavior between ternary operator and if-else inside an always@ block |
|
3 | 1162 | March 24, 2021 |
| Issue with command line synthesis (Ubuntu in VirtualBox) |
|
3 | 1419 | January 6, 2021 |
| Trouble connecting Ubuntu VM |
|
5 | 1736 | January 3, 2021 |
| Beginner Project toggle IO pins |
|
5 | 1746 | December 7, 2020 |
|
Doesn't like clock on pin 3? Routing of Design: Failed
|
|
2 | 1134 | October 10, 2020 |
|
Misunderstanding bitwise OR?
|
|
1 | 893 | April 27, 2020 |
| Further chapters of the book? |
|
1 | 848 | April 27, 2020 |
| Board shows up as unrecognized |
|
1 | 725 | April 27, 2020 |
| Verilog Demo Connections for the Kit |
|
4 | 1354 | February 26, 2020 |
| FPGA board pinout (ShataPlus) |
|
1 | 1829 | October 24, 2019 |
| WebFPGA Documentation book |
|
1 | 1065 | January 14, 2020 |
|
Broken Component?
|
|
1 | 956 | November 6, 2019 |
